CSEM will present their results in the framework of StorAIge at the 31st IEEE International Conference on Electronics Circuits and Systems on 18-20 November 2024 in Nancy (France).
Title of the abstract
A Study on MRAM Across Memory Hierarchies for Edge KWS Adaptive Power Cycling
Authors
Nazareno Sacchi, Erfan Azarkhish, Francesco Caruso, Regis Cattenoz, Petar Jokic, Stephane Emery, Taekwang Jang
Abstract
In edge speech processing, achieving high energy efficiency is crucial for long-term operation on low-power SoC devices. The unpredictable timing and duration of speech events complicate the decision of whether to use off-chip Flash booting or always-on KWS for speech processing. As technology scales below 22 nm, on-chip Flash implementation is challenging, leading to energy-intensive off-chip SPI-Flash booting. For always-on processing, SRAM scratchpad leakage during inactivity consumes significant power. This study investigates the impact of using on-chip MRAM as a) non-volatile memory (NVM) for booting and b) as read-only memory for NN parameters. MRAM as booting NVM reduces the energy consumption for parameter loading compared to booting from off-chip Flash. For time intervals exceeding two seconds between speech events, on-chip MRAM-based power cycling enhances energy efficiency by up to 5x compared to always-on processing and by 40x compared to power cycling with off-chip Flash. Employing on-chip MRAM for NN weight storage improves energy efficiency by 30% over SRAM for a 60 kB RNN, while larger RNNs benefit more from SRAM computation.
For more information: https://epapers2.org/icecs2024/ESR/paper_details.php?paper_id=4104
